As the size (surface area) of integrated circuits has increased and as the number of devices it is possible to form per unit area has increased, it has become possible to incorporate ever-larger circuit networks within integrated circuit chips, which require ever more protection from charge induced defects. Conventional charge protection schemes, such as the incorporation of electrostatic discharge (ESD) protection circuits are directed to protection of the integrated circuit chip after fabrication is complete, but not while the integrated circuit is being fabricated. Therefore, there is a need for new and improved methods and structures to prevent charge induced yield loss during fabrication of integrated circuit chips.